1. Field of the Invention
The present invention is related to the fabrication method of the semeconductor devices, and is related especially to the improved fabrication of the semiconductor devices which form the high-speed, high-integration bipolar transistors by a simple fabrication process of the self-aligned emitter and the base region.
2. Description of the Prior Art
The resistance of the base region, Rb, has to be reduced to enhance the operation speed and the immunity properties from noise of the general bipolar transistor.
The base resistance, Rb, is made up with the resistance R1 of the active base region (or the intrinsic base) under the emitter region and the resistance R2 of the bulk base region from the contact region of the edge part of the emitter region and the bulk base region (or extrinsic base) in a common bipolar transistor.
It is difficult to change the resistance R1 because the area of the intrinsic base region is related closely to the properties of the transistor such as the cutoff frequency, the current gain, etc.
Accordingly, if we intend to reduce the base resistance Rb, the resistance R2 of the bulk base region has to be reduced.
FIG. 1 shows the schematic cross sectional view of the NPN bipolar transistor having the structure that impurities of high-concentration are diffused to the bulk base region to reduce the resistance of the base region.
In FIG. 1, the collector region C is the n-type epitaxial layer formed on the p-type single-crystal silicon substrate, and the base region B the p-type diffusion layer, and the emitter region E the high-concentration n-type diffusion layer.
The insulator film 01 is formed on the substrate in which the collector, the base and the emitter are formed, and each metal electrode 02, 03 and 04 is formed on a part of each region of the emitter E, the base B and the collector C.
The base region B is made up with the p-type region a, the active base region under the emitter, and the region b, the bulk base region of the high-concentration p diffusion layer, and the resistance R.sub.1 of the region a having a high resistance and the resistance R.sub.2 of the region b having a low resistance.
In FIG. 1, the overall base resistance Rb, which is the sum of the resistance R1 and the resistance R2 connected in series, is reduced by reducing the resistance R2 by means of the diffusion of the high-concentration p impurities to the bulk base region b as mentioned before.
When the region a and the region b are formed as above, they are formed by the double ion-implantation process, where it is desirable that the region b should be as close to the emitter region as possible, but not be overlapped.
If the region b is far from the emitter region E, the resistance R1 is to be increased by the extending of the region a.
Also if the region b becomes close and overlapped with the emitter region E, it is degenerated and the leakage current increases and the noise properties become degraded.
The self-align method was applied so that the region b may be as close to the emitter region as possible but may not bring about the degradation phenomenon.
However, there were some disadvantages in this method in the reproducibility of the properties of the NPN transistor because many kinds of complicated processes had to be passed through.
In the mean time, a special equipment which can grow a thick oxide layer without side oxide growing under low temperature is needed to fabricate the NPN transistor which has the shallow emitter width of the desired structure and does not deteriorate the properties.